ANML Documentation

An Overview of Creating and Implementing Automata Networks

ANML and Micron's Automata Processor were specifically designed for creating and implementing automata network designs in hardware. This process is accomplished in two phases: design and runtime.

Figure 1. Compilation of Automata Networks
Automata compilation

Table 1. Phases for Creating and Implementing Automata Networks
Phase Process Tool
Design 1. Construct the network ANML (using the AP Workbench)
2. Simulate and debug AP Workbench
3. Compile AP SDK
Runtime 4. Load the hardware AP SDK
5. Run the design AP SDK

Design Phase

  1. Construct the network

    The first step in creating an automata network is to design and construct the automata. This design and construction can be done with Micron's Automata Processor (AP) Workbench. Other design methodologies can also be used (for example, you can create a design from a set of regular expressions or by writing ANML directly).

  2. Simulate and debug

    After the automata is constructed, the next step is to simulate and debug the design. The AP Workbench contains a simulator where input streams can be created and run against automata designs. The simulator has the ability to single-step forward and backward, and shows which nodes are active and which are not. It also displays report events and the processing cycles at which the report events would be generated.

  3. Compile

    The compilation process takes an automata network and maps it into an abstracted version of the hardware, identifying the hardware resources needed and the routing lines required for connecting these resources to each other given the finite resources contained within the Automata Processor. The output of the compiler is a binary file that can be used to program an Automata Processor.

Runtime Phase

  1. Load the hardware

    After the binary file is complied, the file can be loaded into the Automata Processor using the AP Workbench. (Multiple compiled designs can be loaded onto an Automata Processor if there is capacity to do so. All of the designs will run in parallel on the same input data.)

  2. Run the design

    After the binary file is loaded, the next step is to run the design. The run phase is divided into two steps:

    1. Provide input:
      • Data is presented to the Automata Processor. This is done using DDR3 writes to specific addresses in the address range on the Automata Processor. Input data is buffered in the device, as the Automata Processor processing time will be slower than the DDR3 write speed.
      • Data is processed in the Automata Processor input buffer. Report events may or may not be generated while data processing occurs (this depends on whether the input data stimulates the automata to a reporting state). Assuming report events are generated, these report events are collected into an output buffer within the Automata Processor.
    2. Read and analyze results:
      • The Automata Processor can generate an interrupt when a report event is created. The host system can also poll the processor by reading the device status register.
      • When the host is ready, it can read the report events output buffer by issuing DDR3 read commands to a specific address in the Automata Processor address range.

Tools for Building Automata Networks

The following tools are available for designing, programming, and implementing automata networks within the silicon circuits in an Automata Processor:

Automata Network Markup Language

The Automata Network Markup Language (ANML) is a custom language for describing automata networks. As an XML-based language, any XML or text editor can be used to create automata in ANML. Automata can also be constructed programmatically by having those programs generate ANML output. ANML is fully specified by an XML schema definition (XSD).

Automata Processor Workbench

Micron's Automata Processor (AP) Workbench is a graphical environment for designing and simulating automata networks. The workbench integrates with other software tools to allow designs to be compiled and checked for design errors. The workbench supports the import and export of designs to and from the ANML language. It also contains a Perl Compatible Regular Expression (PCRE) input mechanism where regular expressions can be converted to visual form and used within an automaton.

Automata Processor SDK

The Automata Processor (AP) SDK contains the following applications for programming and operating D480 hardware:

  • AP Compile

    Command line tool used to compile designs into binary form. The tool supports compilation of ANML files. It also supports compilation of PCRE expressions into either binary form or ANML form. Various command line switches can be used to guide the specific operations of the tool.

  • AP Emulate

    Hardware simulator that takes a compiled automaton and a string of input data and runs the input data through the compiled automaton. Report events are generated as output from the simulator. This simulator is independent of the simulator provided with the AP Workbench.

  • AP Admin

    Utility that performs various administrative tasks on a compiled automaton. For example, it can list the properties of the compiled automaton or it can extract a subgraph of the automaton.